The present invention relates to a method for fabricating a semiconductor device, more specifically a method for fabricating a semiconductor device including a multilayer interconnection structure using copper as the main material of the interconnection layers.
As semiconductor devices have been larger scaled and higher integrated, the design rule of the interconnections have been reduced with the generations. Conventionally, the interconnection layers have been formed by depositing interconnection materials and patterning the deposited interconnection materials using lithography and dry etching, but technical limitations in this process commences to arise as the generation has advanced. As a new process for forming the interconnection layers, which takes over the conventional interconnection forming process, the process, the so-called damascene process, of forming a groove pattern and a hole pattern in an inter-layer insulation film and burying an interconnection material in the grooves and the holes, is being used. With the shift in the interconnection forming process, copper (Cu), which has specific resistance lower than aluminum conventionally used as the interconnection material and has superior electro-migration resistance, has come into use.
Semiconductor devices of the multilayer interconnection structure including semiconductor elements, such as transistors, etc., highly integrated by such interconnection forming process is rapidly being developed. Coupled with this, processes of improving the reliability of semiconductor devices by suppressing electro-migration in the interconnection layers or other means have been so far reported (refer to, e.g., Japanese Patent Application Unexamined Publication No. 2000-323476, Japanese Patent Application Unexamined Publication No. 2002-246391 and Japanese Patent Application Unexamined Publication No. 2003-142580).
In operation of a semiconductor device, the device itself generates heat, and its temperature rises. It has been conventionally known that when the multilayer interconnection structure is exposed to high temperature environment due to such temperature rise in operation and the processes following the formation of the multilayer interconnection structure, etc., Cu atoms in the interconnection layers and pores formed in the interconnection layers migrate, forming large voids in the interconnection layers, and these voids causes conduction defects of the interconnection layers.
In the generation where widths of the interconnection layers were 1 μm or more, the widths of the interconnection layers were large enough for sizes of the voids generated in the interconnection layers. Accordingly, the conduction defects due to the voids did not much affect the operation characteristics and reliability of semiconductor devices.
However, in the generation where widths of the interconnection layers is 0.5 μm or less, the influences of the interconnection resistance increase due to voids generated in the interconnection layers on the operation characteristics and reliability of semiconductor devices becomes unignorable. Especially in forming hereafter fine interconnection layers of 0.2 μm or less widths, it is essential to suppress the generation of conduction defects due to the voids.
The above-mentioned Japanese Patent Application Unexamined Publications disclose methods for the purpose of increasing the reliability of semiconductor devices. However, these methods increase the reliability by increasing the resistance to the electro-migration in the interconnection layers. So far, sufficient measures to the conduction defects of the interconnection layers due to voids generated in the interconnection layers left at high temperatures have not been made.